Work in progress, don't take this as The Truth(tm)

Introduction

Given the following two-layer Emitter-Follower (EF) output stage:

there exist good and bad component value choices that affect Total Harmonic Distortion (THD). In this study I examine the THD response of the circuit as it compares with many value combinations. As the values are varied, a few rules of symmetry will always be enforced:

1. VbiasTop1 = VbiasBot1 (Ibias)
2. IdriverTop = IdriverBot (Vbias)
3. R2 = R3 (Re)

This is done because I see no potential for asymmetrical designs to provide better THD readings. The names in brackets will be used throughout the rest of this text to refer to the respective symmetrical component values.

The Big Picture

Let's begin by using the values shown in Fig. 1 and calculate THD as Vbias and Ibias are varied. Since this is the big picture, let's use very generous ranges for Vbias and Ibias:

1. Vbias = 0 -> 15V
2. Ibias = 0 -> 1A

The resulting THD readings of many (Vbias,Ibias) combinations in this range are displayed below:

From this graph it's visible that Ibias has relatively little influence on THD compared to Vbias. As Vbias increases from zero it sharply drops to an area where THD is minimized. Further increase of Vbias forces THD to rise again. Therefore, there looks to be an area of minimal THD right after the initial drop but before the second rise. A look at the same data using a logarithmic THD axis reveals more:

In this log view the seemingly flat area of minimal THD is shown to have non-zero slope. The minimum THD values lie in a trough right after the initial Vbias increase from zero.

The Area of Interest

Let's zoom in on this area of interest. The new ranges are:

1. Vbias = 1.2 -> 2.5V
2. Ibias = 0 -> 1A

Below is the view of this area:

We can now clearly see a double-dip effect. There's a narrow trough of low THD as Vbias increases, followed by a rise in THD, followed by a flat plane of lowest THD. Looking at this data using a logarithmic THD axis is even more revealing:

Notice the slight rise in the surface as Vbias increases from about 2.0 -> 2.5V. This indicates the global minimum of THD is found right after the small hump in the surface. This point however does dissipate more power than points along the narrow trough before the hump, and it offers only marginally better THD performance. If the amplifier application has idle power dissipation/efficiency constraints, it may make sense to sacrifice some THD here and bias your EF stage inside the narrow trough. I'll now consider both cases, starting with the global THD minimum.

The Global THD Minimum Bias Curve

First, let's zoom in on just the global THD minimum area. The new ranges are:

1. Vbias = 1.55 -> 1.95V
2. Ibias = 0 -> 1A

The resulting THD values are plotted below:

The flat plane contains within it the global minimum THD value. However, it's hard to see exactly where this would fall given how flat the plane is. In the next view of this same data the THD axis is kept linear, but the range of THD values shown is only 0.016% -> 0.025%. Any other THD data points are cut right out of the surface. This allows a clearer view of where the actual global THD minimum is:

While still somewhat difficult to see, the global THD minimum point is actually at (Vbias=1.89V,Ibias=990mA) and its value is 0.01735%. This point lies at the extreme of Ibias. If Ibias were increased more, a new lower global THD minimum would most likely be found. Such values of Ibias however are rarely practical. They consume a large amount of power in the driver stage. The corresponding increase in Vbias consumes even more power in the final stage. If the design calls for some power efficiency a good THD-power tradeoff can be made by getting away from high (Ibias,Vbias) values. What makes this a good tradeoff is the gentle slope of the bottom parts of the surface. It's possible to pick a point with half as much Ibias (500mA) and still have essentially the same THD characteristic. It's also possible to have highly similar THD performance with even one quarter (250mA) of the Ibias current. There is of course a point of diminishing returns with these Ibias savings, since eventually the bias point moves up into the back corner and THD starts increasing at a very steep slope (rapidly).

There exists an optimum set of choices for Vbias and Ibias values in this operating region. Where along the curve the EF stage falls is up to the designer and the power budget. Below is a plot of this optimum curve of (Vbias,Ibias) choices:

A better range-constrained view of the same data is shown here:

Note that the bend at the end of the curve where it hits Ibias=1A is not an error. THD values continue dropping for a little bit as Vbias increases even though Ibias is held constant at 1A. There is nothing fundamentally significant here, it's just a reflection of axis ranges chosen in this graph: each step of Vbias is simply more significant than each step of Ibias. Different ranges/steps could be chosen that would allow the curve to terminate without a strange right-angle detour at the end. Moving on.

What is the significance of this curve? How does this set of optimal choices come to be? To answer that it's useful to track:

1. the voltage between the final transistors' bases
2. the voltage across the final emitter resistors
3. the current through the final emitter resistors

as the EF circuit moves through the set of points plotted by the optimal THD curve. These voltages and current must be measured at idle conditions, without any signal applied to the input.

The Power Efficient THD Minimum Bias Curve

The Effect of Re

The Effect of Rload

The Effect of Temperature

The Effect of Signal Amplitude

The Effect of Supply Voltage

The Effect of Frequency

The Effect of Slew Rate

The Effect of Base Stopper Resistors

Final Quiescent (Iqf) Current vs. Load Current (Il)

Is 2nd dip THD minimum when Iqf=Il in some way?

Notes to self:

1. By adjusting Vbias in step with the input waveform in such a way as to keep both output transistors conducting always, it might be possible to achieve a more efficient class-A operation. Corners in the signal may still cause distortion issues. This is similar to Class-H amplification, but different in the fact that there is never a crossover event.
2. Examine THD minimum vs. Oliver optimum V(Re) values. Evaluation of optimum quiescent current, Re, V(Re), and Vb-b ought to all be equivalent given their relationships and complementary nature of the final layer.
3. Plot THD vs. (Vbias,Ibias) tuples.
4. Perform experiments in real silicon to verify results. Must be extremely careful about temperature drift skewing the results. Perhaps using temperature probe on heatsink to verify constant temp control, or to offer correction factor.
5. Re-run simulations with higher source impedance.
6. Examine PSRR of Early effect on drivers, and PSRR of CCSes involved.
7. Examine different Re values and relate final layer quiescent optimum to driver layer quiescent optimum. Individual optimums must be possible indepdently for each layer. Present 2-layer evaluation may be masking further refinement (eg: 0.33 Re may give better results in a 2-layer setup by optimizing final layer independently of driver optimum)